Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : dti_16f_9t_96_and2x1
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.00 60.00

Source File(s) :
/nfs_project/gemini/DV/nadeem/dv/main_reg_14_10_2022/main_reg_excl_ddr_puff_14_10_2022/gemini/design/mem_ss/ddr_ss/../../ip/dti/libs/dti_tm16_phy/hdl/library/dti_tm16ffc_16f96_9t_stdcells_rev1p0p0_pwr.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst36 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst54 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst72 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst89 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst93 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst120 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst121 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst126 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst133 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst134 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst149 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst157 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst174 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst177 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst191 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst192 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst204 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst212 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst224 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst225 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst238 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst252 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst259 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst261 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst267 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst268 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst270 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst271 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst278 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst286 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst288 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst291 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst297 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst315 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst319 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst332 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst339 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst361 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst370 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst372 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst377 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst380 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst387 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst388 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst413 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst426 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst433 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst437 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst439 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst440 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst442 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst443 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst448 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst450 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst453 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst472 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst476 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst485 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst514 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst521 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst531 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst536 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst539 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst547 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst567 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst568 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst569 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst571 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst587 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst595 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst602 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst616 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst623 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst624 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst628 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst633 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst639 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst643 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst693 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst695 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst704 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst705 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst708 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst709 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst714 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst722 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst726 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst733 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst734 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst735 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst745 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst749 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst764 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst767 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst779 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst781 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst786 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst816 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst821 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst824 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst826 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst842 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst849 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst882 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst884 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst902 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst922 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst938 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst940 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst944 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst959 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst964 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst972 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst996 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst997 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst999 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1015 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1019 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1036 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1062 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1078 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1081 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1086 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1117 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1122 0.00 0.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6431 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6434 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6435 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6446 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6449 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6452 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6456 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6458 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6461 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6464 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6470 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6471 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6483 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6485 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6486 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6490 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6499 30.00 30.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6500 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6522 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6528 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6530 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6534 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6571 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6573 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6583 50.00 50.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6586 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6703 0.00 0.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6715 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6718 0.00 0.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6744 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6751 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1940 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1947 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1959 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1977 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1986 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1991 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1994 0.00 0.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2036 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2037 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2053 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2056 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2057 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2090 20.00 20.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5115 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5126 60.00 60.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5143 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5149 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5164 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5169 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5178 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5193 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5205 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5207 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5218 0.00 0.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5228 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5249 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5250 20.00 20.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5271 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5272 0.00 0.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5991 60.00 60.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5998 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6008 50.00 50.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6088 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6091 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6094 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6109 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6119 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6132 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6135 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6141 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6144 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6148 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6153 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6161 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6164 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6167 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6181 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6186 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6188 20.00 20.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6198 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6199 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6202 50.00 50.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6241 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6257 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6275 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6284 20.00 20.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6295 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6302 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6960 50.00 50.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6984 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10299 50.00 50.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11209 20.00 20.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11253 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11254 30.00 30.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11276 60.00 60.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11309 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11313 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11314 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11316 40.00 40.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11333 0.00 0.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11368 10.00 10.00
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config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12531 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12536 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12537 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12540 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12542 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12545 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12546 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12555 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12557 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12558 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12562 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12576 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12591 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12612 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12616 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12617 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12631 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12642 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12652 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12674 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12675 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12708 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12709 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12712 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12713 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12715 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12720 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12721 10.00 10.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12731 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12756 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12768 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12775 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12776 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12778 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12779 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12780 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12783 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12787 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12788 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12791 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12798 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12812 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12825 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12826 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12836 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12852 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12867 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12880 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12887 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12893 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12903 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12904 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12910 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12913 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12914 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12918 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12924 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12925 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12929 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12933 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12939 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12942 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12959 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12960 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12961 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12967 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12973 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12976 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12990 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12992 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13007 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13012 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13026 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13035 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13055 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13056 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13057 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13067 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13081 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13091 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13097 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13099 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13100 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13115 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13117 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13121 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13135 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13137 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13146 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13148 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13150 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13163 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13164 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13171 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13174 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13175 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13177 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13184 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13185 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13189 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13195 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13196 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13198 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13207 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13221 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13222 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13226 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13233 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13241 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13245 0.00 0.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13247 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13248 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13257 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13292 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13300 60.00 60.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13304 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13305 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13311 40.00 40.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13312 20.00 20.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13336 60.00 60.00

Toggle Coverage for Module : dti_16f_9t_96_and2x1
TotalCoveredPercent
Totals 5 3 60.00
Total Bits 10 6 60.00
Total Bits 0->1 5 3 60.00
Total Bits 1->0 5 3 60.00

Ports 5 3 60.00
Port Bits 10 6 60.00
Port Bits 0->1 5 3 60.00
Port Bits 1->0 5 3 60.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
VDD No No No INPUT
VSS No No No INPUT
Z Yes Yes Yes OUTPUT
A Yes Yes Yes INPUT
B Yes Yes Yes INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%